As electronics become more user friendly, the features imposed on the electronics have grown. For example, in a typical hardware product development cycle for an embedded application, algorithm development is done first by algorithm experts. During implementation, engineers translate the design into hardware using an ASIC solution or a using a programmable solution such as a digital signal processor (DSP) core. If this is possible, the designers develop assembly code to target the DSP core using the tools provided by the DSP vendor. As the performance/memory footprint is very important, engineers who understand algorithms and also the micro-architecture and tools of the target DSP need to be employed to develop the firmware.
Porting a floating point algorithm to fixed point number system is a common problem faced in the development of products—especially those that involve the implementation of signal processing algorithms. Unfortunately this effort is often dictated not by the technical merits of a number format representation, but by the availability of processors or perceived cost of implementation. It is important that the number format used during the signal processing stage be chosen well so as to realize the gain expected from the system. Much work has been done in converting a floating point system model to fixed point system implementation on an off the shelf DSP. This is usually the case as the system designer does not have the flexibility of choosing the ALU width in the DSP. The system designer has to accept what is given (or available) and port the system from a floating point model to the number representation supported by the DSP.
The benefits and trade-offs associated with fixed and floating point representation are the subject of many debates. The differences in fixed point number system and floating point number system over a given signal range is given in the examples shown in FIGS. 1A-1B and discussed next.
Turning now to FIG. 1A, if the number format representation is limited to N bits, the system can perform 2N possible representations. If the range of signal power (and hence amplitude) at the input is spread over x dB, and for the sake of simplicity, if there is a uniform gain through the system so that the output signal spread (and signal spread at any point in the system) is over the same x dB. Then the 2N representations can be uniformly distributed over this range of x dB. The hardware cost of the system reduces as N is decreased. However, this leads to fewer bins and more quantization errors. One classical method of countering this problem in typical communication systems uses scaling. While the static range of the input signal could be quite large, the dynamic range of the signal over the time constant of the system is only a fraction of that. So, by employing suitable scaling, it is possible to limit the range represented by our number system to a small fraction of x dB. This operation is conventionally done by the system designer with due consideration since scaling introduces the potential of rounding noise in addition to the quantization noise.
FIG. 1B shows an exemplary case where the same N bits are used in a floating point scheme. If k bits are used for exponent and n−k bits are used for mantissa, the representation becomes quite complex to render in a single figure (as done for fixed point). However, if the representation is chosen well, it is possible to have a format where 2^(n−k) bits of mantissa cover any given dynamic range of the signal and 2^k such range bins exist in the signal spread. For example, if the signal spread is 80 dB and this range can be safely divided into eight 10 dB bins, then 3 bits are needed for the exponent and the remaining n-3 bits can be used for the mantissa. This is represented in FIG. 1B.
During development, a designer crafts a system model or algorithm to solve a particular problem. Usually, the first system model is expressed in floating point to avoid quantization and rounding noise issues. After the system model has been developed, the system designer then converts the model, code or algorithm into an implementation for a particular architecture whose fixed/floating point characteristics are pre-specified. When the system designer considers fixed point implementations, the scaling points and scaling algorithms have to be manually defined. This is often done without a precise idea of the hardware of computational cost of such methods. When a floating point representation different from the model is chosen form implementation, the system designer has no control over the bits used for exponent or mantissa and hence has to deal with a sub-optimal representation format.